This invention relates generally to integrated circuits and in particular to a memory address and decode circuits with ultra thin body transistors.
Modern electronic systems typically include a data storage device such as a dynamic random access memory (DRAM), static random access memory (SRAM), video random access memory (VRAM), erasable programmable read only memory (EPROM), flash memory, or other conventional memory device. As these systems become more sophisticated, they require more and more memory in order to keep pace with the increasing complexity of software based applications that run on the systems. Thus, as the technology relating to memory devices has evolved, designers have tried to increase the density of the components of the memory device. For example, the electronics industry strives to decrease the size of memory cells that store the data in the memory device. This allows a larger number of memory cells to be fabricated without substantially increasing the size of the semiconductor wafer used to fabricate the memory device.
Memory devices store data in vast arrays of memory cells. Essentially, the cells are located at intersections of wordlines and bitlines (rows and columns of an array). Each cell conventionally stores a single bit of data as a logical xe2x80x9c1xe2x80x9d or a logical xe2x80x9c0xe2x80x9d and can be individually accessed or addressed. Conventionally, each cell is addressed using two multi-bit numbers. The first multi-bit number, or row address, identifies the row of the memory array in which the memory cell is located. The second multi-bit number, or column address, identifies the column of the memory array in which the desired memory cell is located. Each row address/column address combination corresponds to a single memory cell.
To access an individual memory cell, the row and column addresses are applied to inputs of row and column decoders, respectively. Conventionally, row and column decoders are fabricated using programmable logic arrays. These arrays are configured so as to select desired word and bit lines based on address signals applied to the inputs of the array. As with the array of memory cells, the decoder arrays use a portion of the surface area of the semiconductor wafer. Thus, designers also strive to reduce the surface area required for the decoder arrays.
Memory devices are fabricated using photolithographic techniques that allow semiconductor and other materials to be manipulated to form integrated circuits as is known in the art. These photolithographic techniques essentially use light that is focussed through lenses and masks to define patterns in the materials with microscopic dimensions. The equipment and techniques that are used to implement this photolithography provide a limit for the size of the circuits that can be formed with the materials. Essentially, at some point, the lithography cannot create a fine enough image with sufficient clarity to decrease the size of the elements of the circuit. In other words, there is a minimum dimension that can be achieved through conventional photolithography. This minimum dimension is referred to as the xe2x80x9ccritical dimensionxe2x80x9d (CD) or minimum xe2x80x9cfeature sizexe2x80x9d (F) of the photolithographic process. The minimum feature size imposes one constraint on the size of the components of a memory device, including the decoder array. In order to keep up with the demands for higher capacity memory devices, designers search for other ways to reduce the size of the components of the memory device, including the decoder array.
As the density requirements become higher and higher in gigabit DRAMs and beyond, it becomes more and more crucial to minimize device area. The NOR address decode circuit is one example of an architecture for row and column decoders.
The continuous scaling, however, of MOSFET technology to the deep sub-micron region where channel lengths are less than 0.1 micron, 100 mn, or 1000 A causes significant problems in the conventional transistor structures. As shown in FIG. 1, junction depths should be much less than the channel length of 1000 A, or this implies junction depths of a few hundred Angstroms. Such shallow junctions are difficult to form by conventional implantation and diffusion techniques. Extremely high levels of channel doping are required to suppress short-channel effects such as drain-induced barrier lowering; threshold voltage roll off, and sub-threshold conduction. Sub-threshold conduction is particularly problematic in DRAM technology as it reduces the charge storage retention time on the capacitor cells. These extremely high doping levels result in increased leakage and reduced carrier mobility. Thus making the channel shorter to improve performance is negated by lower carrier mobility.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for memory address and decode circuits that use less surface area of a semiconductor wafer as compared to conventional decoder arrays.
The above mentioned problems with decoder arrays and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A circuit and method for a decoder array using ultra thin body vertical transistors is provided.
In particular, one embodiment of the present invention provides a decoder for a memory device. The decoder includes a number of address lines and a number of output lines. The address lines and the output lines form an array. The decoder includes a number of vertical pillars extending outwardly from a semiconductor substrate at intersections of output lines and address lines. Each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer. The decoder further includes a number of single crystalline ultra thin vertical transistor that are selectively disposed adjacent the number of vertical pillars. Each single crystalline vertical transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, and an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions. A plurality of buried source lines formed of single crystalline semiconductor material are disposed below the pillars in the array for interconnecting with the first contact layer of pillars in the array. And, each of the number of address lines is disposed in a trench between rows of the pillars for addressing the ultra thin single crystalline vertical body regions of the single crystalline vertical transistors that are adjacent to the trench.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.